-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : upcounter_nbit_tester_upcountertester.vhd =
-- = Notes   : BikeCom.UpCounter_NBit_tester             =
-- =======================================================
-- = Datum   : 05.03.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Architecture BikeCom.UpCounter_NBit_tester.interface
--

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY UpCounter_NBit_tester IS
   PORT( 
      CountOut : IN     std_logic_vector (11 DOWNTO 0) ;
      EnCnt    : OUT    std_logic  ;
      Reset    : OUT    std_logic 
   );

-- Declarations

END UpCounter_NBit_tester ;

ARCHITECTURE Behavioral OF UpCounter_NBit_tester IS
CONSTANT clk_prd : time := 1 ms;
SIGNAL tmp_clk : std_logic := '0';
BEGIN
  Reset     <= '1',
               '0' AFTER 50 ms,
		       '1' AFTER 60 ms;
  EnCnt     <= '1',
               '0' AFTER 100 ms,
		       '1' AFTER 120 ms,
			   '0' AFTER 250 ms,
			   '1' AFTER 300 ms;
END Behavioral;