-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : UpCounter_NBit_tb.vhd                     =
-- = Notes   : BikeCom.UpCounter_NBit_tb                 =
-- =======================================================
-- = Datum   : 08.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Entity BikeCom.UpCounter_NBit_tb.symbol
--

ENTITY UpCounter_NBit_tb IS
-- Declarations

END UpCounter_NBit_tb ;

--
-- VHDL Architecture BikeCom.UpCounter_NBit_tb.struct
--

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY BikeCom;

ARCHITECTURE struct OF UpCounter_NBit_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL Clock_10ms : std_logic;
   SIGNAL CountOut   : std_logic_vector(11 DOWNTO 0);
   SIGNAL EnCnt      : std_logic;
   SIGNAL Reset      : std_logic;

   -- Component Declarations
   COMPONENT Clock_Generator
   GENERIC (
      ClkPeriod : Time := 10 ms
   );
   PORT (
      ResetClock : IN     std_logic ;
      Clock      : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT UpCounter_NBit
   GENERIC (
      N : Positive := 16
   );
   PORT (
      Clock    : IN     std_logic ;
      EnCnt    : IN     std_logic ;
      Reset    : IN     std_logic ;
      CountOut : OUT    std_logic_vector ((N - 1) DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT UpCounter_NBit_tester
   PORT (
      CountOut : IN     std_logic_vector (11 DOWNTO 0);
      EnCnt    : OUT    std_logic ;
      Reset    : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : Clock_Generator USE ENTITY BikeCom.Clock_Generator;
   FOR ALL : UpCounter_NBit USE ENTITY BikeCom.UpCounter_NBit;
   FOR ALL : UpCounter_NBit_tester USE ENTITY BikeCom.UpCounter_NBit_tester;
   -- pragma synthesis_on

BEGIN
   -- Instance port mappings.
   I2 : Clock_Generator
      GENERIC MAP (
         ClkPeriod => 10 ms
      )
      PORT MAP (
         ResetClock => Reset,
         Clock      => Clock_10ms
      );
   I0 : UpCounter_NBit
      GENERIC MAP (
         N => 12
      )
      PORT MAP (
         Clock    => Clock_10ms,
         EnCnt    => EnCnt,
         Reset    => Reset,
         CountOut => CountOut
      );
   I1 : UpCounter_NBit_tester
      PORT MAP (
         CountOut => CountOut,
         EnCnt    => EnCnt,
         Reset    => Reset
      );

END struct;