-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : upcounter_nbit_behavioral.vhd             =
-- = Notes   : BikeCom.UpCounter_NBit                    =
-- =======================================================
-- = Datum   : 21.03.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Architecture BikeCom.UpCounter_NBit.symbol
--

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY UpCounter_NBit IS
   GENERIC( 
      N : Positive := 16
   );
   PORT( 
      Clock    : IN     std_logic  ;
      EnCnt    : IN     std_logic  ;
      Reset    : IN     std_logic  ;
      CountOut : OUT    std_logic_vector ((N - 1) DOWNTO 0)
   );

-- Declarations

END UpCounter_NBit ;

ARCHITECTURE Behavioral OF UpCounter_NBit IS
  SIGNAL int_count : std_logic_vector((N -1) DOWNTO 0);
BEGIN
  vhdl_intcount : PROCESS (Clock, Reset, int_count)   
  BEGIN
    IF Reset = '0' THEN
      int_count <= (OTHERS => '0');
	ELSE
	  IF RISING_EDGE(Clock) THEN
	    IF EnCnt = '1' THEN
  	      int_count <= unsigned(int_count) + 1 ;
        ELSE
          NULL ;
	    END IF;
      END IF;
	END IF;  
  END PROCESS vhdl_intcount;
  CountOut <= int_count;
END Behavioral;