-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : system_clock_generator_flow.vhd           =
-- = Notes   : BikeCom.System_Clock_Generator            =
-- =======================================================
-- = Datum   : 07.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Entity BikeCom.System_Clock_Generator.symbol
--

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY System_Clock_Generator IS
   GENERIC( 
      ClockPeriod : Time := 305175 ps
   );
   PORT( 
      SystemClock : OUT    std_logic 
   );

-- Declarations

END System_Clock_Generator ;

--
-- VHDL Architecture BikeCom.System_Clock_Generator.flow
--

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ARCHITECTURE flow OF System_Clock_Generator IS

   -- Architecture declarations
   CONSTANT sys_clk_prd : time := ClockPeriod;
   SIGNAL sys_clk_tmp : std_logic := '0';

BEGIN

   ---------------------------------------------------------------------------
   process0 : PROCESS (sys_clk_tmp)
   ---------------------------------------------------------------------------
   BEGIN
      sys_clk_tmp <= NOT sys_clk_tmp AFTER sys_clk_prd / 2;
      SystemClock <= sys_clk_tmp;
   END PROCESS process0;


END flow;