-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : multiplierseq_behavioral.vhd              =
-- = Notes   : BikeCom.MultiplierSeq                     =
-- =======================================================
-- = Datum   : 18.02.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Architecture BikeCom.MultiplierSeq.symbol
--

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;

entity MultiplierSeq is
   port (
      clk   : in std_logic;
      rst   : in std_logic;
      start : in std_logic;
      A_in  : in std_logic_vector(16 downto 0);
      B_in  : in std_logic_vector(16 downto 0);
      done  : out std_logic;
      error : out std_logic;
      C_out : out std_logic_vector(16 downto 0));
end MultiplierSeq;

architecture behavioral of MultiplierSeq is

--Registers
signal P       : std_logic_vector(17 downto 0);
signal result  : std_logic_vector(17 downto 0);
signal A       : std_logic_vector(16 downto 0);
signal B       : std_logic_vector(16 downto 0);

signal count   : std_logic_vector(4 downto 0);

--Control signals
signal load_en : std_logic;
signal mul_en  : std_logic;

--State machine related signals
signal STATE            : std_logic_vector(4 downto 0);
signal NEXT_STATE       : std_logic_vector(4 downto 0);
constant WAIT_FOR_START : std_logic_vector(4 downto 0) := "00001";
constant LOAD           : std_logic_vector(4 downto 0) := "00010";
constant MULTIPLY       : std_logic_vector(4 downto 0) := "00100";
constant FINISH         : std_logic_vector(4 downto 0) := "01000";
constant OVERFLOW       : std_logic_vector(4 downto 0) := "10000";

begin

C_out <= result(16 downto 0);
load_en <= STATE(1);
mul_en <= STATE(2);
done <= STATE(3);
error <= STATE(4);

process(clk, rst)
   begin
      if (rst = '0') then
         B <= (OTHERS => '0');
      elsif(clk'event and clk = '1') then
         if (load_en = '1') then
            B <= B_in;
		 elsif (mul_en = '1') then
		    B <= '0' & B(16 downto 1);
         end if;
      end if;
   end process;

process(clk, rst)
   begin
      if (rst = '0') then
         A <= (OTHERS => '0');
      elsif(clk'event and clk = '1') then
         if (load_en = '1') then
            A <= A_in;
         elsif (mul_en = '1') then
            A <= A(15 downto 0) & '0';
         end if;
      end if;
   end process;

process(clk, rst)
   begin
      if (rst = '0') then
         P <= (OTHERS => '0');
      elsif(clk'event and clk = '1') then
         if (load_en = '1') then
            P <= (OTHERS => '0');
         elsif (mul_en = '1') then
            P <= (result(17) OR A(16)) & result(16 downto 0);
         end if;
      end if;
   end process;

process(P, A, B)
   begin
      if B(0) = '1' then
        result <= P + ("0" & A);
	  else
	    result <= P;
	  end if;
   end process;

process(clk, rst)
   begin
      if(rst = '0') then
         STATE <= WAIT_FOR_START;
      elsif(clk'event and clk = '1') then
         STATE <= NEXT_STATE;
      end if;
   end process;

process(STATE, start, count, Result, B)
   begin
      case STATE is
         when WAIT_FOR_START =>
            if start = '1' then
               NEXT_STATE <= LOAD;
            else
               NEXT_STATE <= WAIT_FOR_START;
            end if;
         when LOAD => NEXT_STATE <= MULTIPLY;
		 when MULTIPLY =>
		    if (Result(17) = '1' AND B(0) = '1') then
			   NEXT_STATE <= OVERFLOW;
            elsif count = "00000" then
               NEXT_STATE <= FINISH;
            else
               NEXT_STATE <= MULTIPLY;
            end if;
		 when OVERFLOW => NEXT_STATE <= WAIT_FOR_START;
		 when FINISH => NEXT_STATE <= WAIT_FOR_START;
         when others => NEXT_STATE <= WAIT_FOR_START;
      end case;
   end process;

process(clk, rst, start)
   begin
      if (start = '1') THEN
		count <= "10000";
	  elsif(rst = '0') then
         count <= "10000";
      elsif(clk'event and clk = '1') then
         if(mul_en = '1') then
            count <= count - "00001";
         end if;
      end if;
   end process;

end behavioral;