-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : latch_tester_flow.vhd                     =
-- = Notes   : BikeCom.Latch_tester                      =
-- =======================================================
-- = Datum   : 08.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Entity BikeCom.Latch_tester.interface
--

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Latch_tester IS
   PORT( 
      Data_Out : IN     std_logic_vector (15 DOWNTO 0) ;
      Data_In  : OUT    std_logic_vector (15 DOWNTO 0) ;
      Load     : OUT    std_logic  ;
      Reset    : OUT    std_logic 
   );

-- Declarations

END Latch_tester ;

--
-- VHDL Architecture BikeCom.Latch_tester.flow
--

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ARCHITECTURE flow OF Latch_tester IS

BEGIN

   ---------------------------------------------------------------------------
   process0 : PROCESS
   ---------------------------------------------------------------------------
   BEGIN
      Reset <= '0',
                    '1' AFTER 1 ms,
                    '0' AFTER 10 ms,
                    '1' AFTER 11 ms;
      
      Data_In <= "0000000000000000",
                        "0001000000000000" AFTER 4 ms,
                        "0000000100000000" AFTER 15 ms;
      
      Load <= '0',
                    '1' AFTER 6 ms,
                    '0' AFTER 7 ms,
                    '1' AFTER 16 ms,
                    '0' AFTER 17 ms;
      wait;
   END PROCESS process0;


END flow;