-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : latch_tb_struct.vhd                       =
-- = Notes   : BikeCom.Latch_tb                          =
-- =======================================================
-- = Datum   : 08.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Entity BikeCom.Latch_tb.symbol
--

ENTITY Latch_tb IS
-- Declarations

END Latch_tb ;

--
-- VHDL Architecture BikeCom.Latch_tb.struct
--

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY BikeCom;

ARCHITECTURE struct OF Latch_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL Data_In     : std_logic_vector(15 DOWNTO 0);
   SIGNAL Data_Out    : std_logic_vector(15 DOWNTO 0);
   SIGNAL Load        : std_logic;
   SIGNAL Reset       : std_logic;
   SIGNAL SystemClock : std_logic;

   -- Component Declarations
   COMPONENT Latch
   GENERIC (
      N : Positive := 16
   );
   PORT (
      Clock    : IN     std_logic ;
      Data_In  : IN     std_logic_vector ((N-1) DOWNTO 0);
      Load     : IN     std_logic ;
      Reset    : IN     std_logic ;
      Data_Out : OUT    std_logic_vector ((N-1) DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT Latch_tester
   PORT (
      Data_Out : IN     std_logic_vector (15 DOWNTO 0);
      Data_In  : OUT    std_logic_vector (15 DOWNTO 0);
      Load     : OUT    std_logic ;
      Reset    : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT System_Clock_Generator
   GENERIC (
      ClockPeriod : Time := 305175 ps
   );
   PORT (
      SystemClock : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : Latch USE ENTITY BikeCom.Latch;
   FOR ALL : Latch_tester USE ENTITY BikeCom.Latch_tester;
   FOR ALL : System_Clock_Generator USE ENTITY BikeCom.System_Clock_Generator;
   -- pragma synthesis_on

BEGIN
   -- Instance port mappings.
   I0 : Latch
      GENERIC MAP (
         N => 16
      )
      PORT MAP (
         Clock    => SystemClock,
         Data_In  => Data_In,
         Load     => Load,
         Reset    => Reset,
         Data_Out => Data_Out
      );
   I1 : Latch_tester
      PORT MAP (
         Data_Out => Data_Out,
         Data_In  => Data_In,
         Load     => Load,
         Reset    => Reset
      );
   I2 : System_Clock_Generator
      GENERIC MAP (
         ClockPeriod => 1 ms
      )
      PORT MAP (
         SystemClock => SystemClock
      );

END struct;