-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : latch_behavioral.vhd                      =
-- = Notes   : BikeCom.Latch                             =
-- =======================================================
-- = Datum   : 21.03.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Architecture BikeCom.Latch.symbol
--

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Latch IS
   GENERIC( 
      N : Positive := 16
   );
   PORT( 
      Clock    : IN     std_logic  ;
      Data_In  : IN     std_logic_vector ((N-1) DOWNTO 0) ;
      Load     : IN     std_logic  ;
      Reset    : IN     std_logic  ;
      Data_Out : OUT    std_logic_vector ((N-1) DOWNTO 0)
   );

-- Declarations

END Latch ;

ARCHITECTURE behavioral OF Latch IS
SIGNAL reg : std_logic_vector ((N-1) DOWNTO 0);

BEGIN
PROCESS (Clock, Data_In, Load, Reset)
  BEGIN
	IF Reset = '0' THEN
	  reg <= (OTHERS => '0');
	ELSIF RISING_EDGE (Clock) THEN
	  IF Load = '1' THEN
	    reg <= Data_In;
	  END IF;
	END IF;
  END PROCESS;

Data_Out <= reg;
	  
END behavioral;