-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : dividerseq_tester_flow.vhd                =
-- = Notes   : BikeCom.DividerSeq_tester                 =
-- =======================================================
-- = Datum   : 07.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Entity BikeCom.DividerSeq_tester.interface
--

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY DividerSeq_tester IS
   PORT( 
      C_out : IN     std_logic_vector (16 DOWNTO 0) ;
      done  : IN     std_logic  ;
      error : IN     std_logic  ;
      A_in  : OUT    std_logic_vector (16 DOWNTO 0) ;
      B_in  : OUT    std_logic_vector (16 DOWNTO 0) ;
      rst   : OUT    std_logic  ;
      start : OUT    std_logic 
   );

-- Declarations

END DividerSeq_tester ;

--
-- VHDL Architecture BikeCom.DividerSeq_tester.flow
--

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ARCHITECTURE flow OF DividerSeq_tester IS

BEGIN

   ---------------------------------------------------------------------------
   process0 : PROCESS
   ---------------------------------------------------------------------------
   BEGIN
      rst <= '1',
               '0' AFTER 1 ms,
               '1' AFTER 2 ms;
      A_in <= "11111111111111111",
                   "01001000000000000" AFTER 5 ms,
                   "00001011000100000" AFTER 40 ms,
                   "00000000001100111" AFTER 90 ms,
                   "10110101000000000" AFTER 140 ms,
                   "10011100000001100" AFTER 190 ms;
      B_in <= "11111111111111111",
                   "00000000000011100" AFTER 5 ms,
                   "00000010110000000" AFTER 40 ms,
                   "00000000000001011" AFTER 90 ms,
                   "00000000010100000" AFTER 140 ms,
                   "00000000000000000" AFTER 190 ms;
      start <= '0',
                  '1' AFTER 6 ms,
                  '0' AFTER 7 ms,
                  '1' AFTER 41 ms,
                  '0' AFTER 42 ms,
                  '1' AFTER 91 ms,
                  '0' AFTER 92 ms,
                  '1' AFTER 141 ms,
                  '0' AFTER 142 ms,
                  '1' AFTER 191 ms,
                  '0' AFTER 192 ms;
      wait;
   END PROCESS process0;


END flow;