-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : dividerseq_tb_struct.vhd                  =
-- = Notes   : BikeCom.DividerSeq_tb                     =
-- =======================================================
-- = Datum   : 07.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Entity BikeCom.DividerSeq_tb.symbol
--

ENTITY DividerSeq_tb IS
-- Declarations

END DividerSeq_tb ;

--
-- VHDL Architecture BikeCom.DividerSeq_tb.struct
--

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY BikeCom;

ARCHITECTURE struct OF DividerSeq_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL A_in        : std_logic_vector(16 DOWNTO 0);
   SIGNAL B_in        : std_logic_vector(16 DOWNTO 0);
   SIGNAL C_out       : std_logic_vector(16 DOWNTO 0);
   SIGNAL SystemClock : std_logic;
   SIGNAL done        : std_logic;
   SIGNAL error       : std_logic;
   SIGNAL rst         : std_logic;
   SIGNAL start       : std_logic;

   -- Component Declarations
   COMPONENT DividerSeq
   PORT (
      A_in  : IN     std_logic_vector (16 DOWNTO 0);
      B_in  : IN     std_logic_vector (16 DOWNTO 0);
      clk   : IN     std_logic ;
      rst   : IN     std_logic ;
      start : IN     std_logic ;
      C_out : OUT    std_logic_vector (16 DOWNTO 0);
      done  : OUT    std_logic ;
      error : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT DividerSeq_tester
   PORT (
      C_out : IN     std_logic_vector (16 DOWNTO 0);
      done  : IN     std_logic ;
      error : IN     std_logic ;
      A_in  : OUT    std_logic_vector (16 DOWNTO 0);
      B_in  : OUT    std_logic_vector (16 DOWNTO 0);
      rst   : OUT    std_logic ;
      start : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT System_Clock_Generator
   GENERIC (
      ClockPeriod : Time := 305175 ps
   );
   PORT (
      SystemClock : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : DividerSeq USE ENTITY BikeCom.DividerSeq;
   FOR ALL : DividerSeq_tester USE ENTITY BikeCom.DividerSeq_tester;
   FOR ALL : System_Clock_Generator USE ENTITY BikeCom.System_Clock_Generator;
   -- pragma synthesis_on

BEGIN
   -- Instance port mappings.
   I0 : DividerSeq
      PORT MAP (
         A_in  => A_in,
         B_in  => B_in,
         clk   => SystemClock,
         rst   => rst,
         start => start,
         C_out => C_out,
         done  => done,
         error => error
      );
   I1 : DividerSeq_tester
      PORT MAP (
         C_out => C_out,
         done  => done,
         error => error,
         A_in  => A_in,
         B_in  => B_in,
         rst   => rst,
         start => start
      );
   I2 : System_Clock_Generator
      GENERIC MAP (
         ClockPeriod => 1 ms
      )
      PORT MAP (
         SystemClock => SystemClock
      );

END struct;