-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : clock_generator_flow.vhd                  =
-- = Notes   : BikeCom.Clock_Generator                   =
-- =======================================================
-- = Datum   : 08.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Entity BikeCom.Clock_Generator.symbol
--

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Clock_Generator IS
   GENERIC( 
      ClkPeriod : Time := 10 ms
   );
   PORT( 
      ResetClock : IN     std_logic  ;
      Clock      : OUT    std_logic 
   );

-- Declarations

END Clock_Generator ;

--
-- VHDL Architecture BikeCom.Clock_Generator.flow
--

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ARCHITECTURE flow OF Clock_Generator IS

   -- Architecture declarations
   SIGNAL clk_tmp : std_logic := '0';

BEGIN

   ---------------------------------------------------------------------------
   process0 : PROCESS (ResetClock, clk_tmp)
   ---------------------------------------------------------------------------
   BEGIN
      IF Falling_Edge (ResetClock) THEN
         clk_tmp <= '1';
         Clock <= clk_tmp;
      END IF;
      clk_tmp <= NOT clk_tmp AFTER ClkPeriod;
      Clock <= clk_tmp;
   END PROCESS process0;


END flow;