-- University of Applied Sciences / Munich -- Federal Technological Education Center / Rio de Janeiro -- ======================================================= -- = Project : Bicycle computer in VHDL = -- = File : bin2bcdconvseq_tester_flow.vhd = -- = Notes : BikeCom.Bin2BcdConvSeq_tester = -- ======================================================= -- = Datum : 08.08.2001 = -- = Design : Joachim Reiss = -- = Revision: 001 = -- ======================================================= -- -- -- -- VHDL Entity BikeCom.Bin2BcdConvSeq_tester.interface -- LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Bin2BcdConvSeq_tester IS PORT( Bcd_out : IN std_logic_vector (19 DOWNTO 0) ; Comp_out : IN natural ; done : IN std_logic ; error : IN std_logic ; Bin_in : OUT std_logic_vector (16 DOWNTO 0) ; rst : OUT std_logic ; start : OUT std_logic ); -- Declarations END Bin2BcdConvSeq_tester ; -- -- VHDL Architecture BikeCom.Bin2BcdConvSeq_tester.flow -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ARCHITECTURE flow OF Bin2BcdConvSeq_tester IS BEGIN --------------------------------------------------------------------------- process0 : PROCESS --------------------------------------------------------------------------- BEGIN rst <= '1', '0' AFTER 1 ms, '1' AFTER 2 ms; Bin_in <= "00000000000000000", "00010000101000101" AFTER 5 ms, "10000110110101100" AFTER 50 ms, "11000011010100000" AFTER 100 ms; start <= '0', '1' AFTER 6 ms, '0' AFTER 7 ms, '1' AFTER 51 ms, '0' AFTER 52 ms, '1' AFTER 101 ms, '0' AFTER 102 ms; wait; END PROCESS process0; END flow;