-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : bin2bcdconvseq_tb_struct.vhd              =
-- = Notes   : BikeCom.Bin2BcdConvSeq_tb                 =
-- =======================================================
-- = Datum   : 08.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Entity BikeCom.Bin2BcdConvSeq_tb.symbol
--

ENTITY Bin2BcdConvSeq_tb IS
-- Declarations

END Bin2BcdConvSeq_tb ;

--
-- VHDL Architecture BikeCom.Bin2BcdConvSeq_tb.struct
--

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY BikeCom;

ARCHITECTURE struct OF Bin2BcdConvSeq_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL Bcd_out     : std_logic_vector(19 DOWNTO 0);
   SIGNAL Bin_in      : std_logic_vector(16 DOWNTO 0);
   SIGNAL Comp_out    : natural;
   SIGNAL SystemClock : std_logic;
   SIGNAL done        : std_logic;
   SIGNAL error       : std_logic;
   SIGNAL rst         : std_logic;
   SIGNAL start       : std_logic;

   -- Component Declarations
   COMPONENT Bin2BcdConvSeq
   PORT (
      clk      : IN     std_logic ;
      rst      : IN     std_logic ;
      start    : IN     std_logic ;
      done     : OUT    std_logic ;
      error    : OUT    std_logic ;
      Bcd_out  : OUT    std_logic_vector (19 DOWNTO 0);
      Bin_in   : IN     std_logic_vector (16 DOWNTO 0);
      Comp_out : OUT    natural 
   );
   END COMPONENT;
   COMPONENT Bin2BcdConvSeq_tester
   PORT (
      Bcd_out  : IN     std_logic_vector (19 DOWNTO 0);
      Comp_out : IN     natural ;
      done     : IN     std_logic ;
      error    : IN     std_logic ;
      Bin_in   : OUT    std_logic_vector (16 DOWNTO 0);
      rst      : OUT    std_logic ;
      start    : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT System_Clock_Generator
   GENERIC (
      ClockPeriod : Time := 305175 ps
   );
   PORT (
      SystemClock : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : Bin2BcdConvSeq USE ENTITY BikeCom.Bin2BcdConvSeq;
   FOR ALL : Bin2BcdConvSeq_tester USE ENTITY BikeCom.Bin2BcdConvSeq_tester;
   FOR ALL : System_Clock_Generator USE ENTITY BikeCom.System_Clock_Generator;
   -- pragma synthesis_on

BEGIN
   -- Instance port mappings.
   I0 : Bin2BcdConvSeq
      PORT MAP (
         clk      => SystemClock,
         rst      => rst,
         start    => start,
         done     => done,
         error    => error,
         Bcd_out  => Bcd_out,
         Bin_in   => Bin_in,
         Comp_out => Comp_out
      );
   I1 : Bin2BcdConvSeq_tester
      PORT MAP (
         Bcd_out  => Bcd_out,
         Comp_out => Comp_out,
         done     => done,
         error    => error,
         Bin_in   => Bin_in,
         rst      => rst,
         start    => start
      );
   I2 : System_Clock_Generator
      GENERIC MAP (
         ClockPeriod => 1 ms
      )
      PORT MAP (
         SystemClock => SystemClock
      );

END struct;