-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : bin2bcdconvseq_behavioral.vhd             =
-- = Notes   : BikeCom.Bin2BcdConvSeq                    =
-- =======================================================
-- = Datum   : 07.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Architecture BikeCom.Bin2BcdConvSeq.symbol
--

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Bin2BcdConvSeq IS
   PORT( 
      clk      : IN     std_logic  ;
      rst      : IN     std_logic  ;
      start    : IN     std_logic  ;
      done     : OUT    std_logic  ;
      error    : OUT    std_logic  ;
      Bcd_out  : OUT    std_logic_vector (19 DOWNTO 0) ;
      Bin_in   : IN     std_logic_vector (16 DOWNTO 0) 
   );

-- Declarations

END Bin2BcdConvSeq ;

ARCHITECTURE Behavioral OF Bin2BcdConvSeq IS

--Type Declaration
subtype counter is natural range 0 to 20;
type integer_array is array (20 downto 0) of natural;

--Registers
signal P            : std_logic_vector(19 downto 0);
signal Q            : std_logic_vector(16 downto 0);
signal tbin         : std_logic_vector(16 downto 0);
signal Bcd          : std_logic_vector(19 downto 0);
signal count        : counter;

-- Constant declaration
constant Init_Value   : integer_array :=
           (
		      ( 80000, 40000, 20000, 10000,
				 8000,  4000,  2000,  1000,
				  800,   400,   200,   100,
				   80,    40,	 20,	10,
					8,	   4,	  2,	 1,    0)
		    );

--Control signals
signal load_en : std_logic;
signal conv_en  : std_logic;
		  
--State machine related signals
signal STATE            : std_logic_vector(4 downto 0);
signal NEXT_STATE       : std_logic_vector(4 downto 0);
constant WAIT_FOR_START : std_logic_vector(4 downto 0) := "00001";
constant LOAD           : std_logic_vector(4 downto 0) := "00010";
constant CONVERT        : std_logic_vector(4 downto 0) := "00100";
constant FINISH         : std_logic_vector(4 downto 0) := "01000";
constant OUTOFRANGE     : std_logic_vector(4 downto 0) := "10000";


BEGIN

Bcd_out <= bcd;
Comp_out <= Init_value (count);
load_en <= STATE(1);
conv_en <= STATE(2);
done <= STATE(3);
error <= STATE(4);

process(clk, rst)
   begin
     if (rst = '0') then
        tbin <= (OTHERS => '0');
     elsif(clk'event and clk = '1') then
        if (load_en = '1') then
          tbin <= unsigned(Bin_in) + 1;
		elsif (conv_en = '1') then
           if (unsigned(tbin) > Init_Value(count)) then
			 tbin <= unsigned(Q) - Init_Value(count);
		   else
		     tbin <= Q;
		   end if;
        end if;
	 end if;
   end process;

process(clk, rst, tbin)
   begin
      if (rst = '0') then
         P <= (OTHERS => '0');
      elsif(clk'event and clk = '1') then
         if (load_en = '1') then
            P <= "00000000000000000000";
         elsif (conv_en = '1') then
           if (unsigned(Q) > Init_Value(count)) then
			 P <= bcd(18 downto 0) & '1';
		   else
	 	     P <= bcd(18 downto 0) & '0';
		   end if;
         end if;
       end if;
   end process;

process(tbin, P)
   begin
   	 bcd <= P;
	 Q <= tbin;
   end process;

process(clk, rst)
   begin
      if(rst = '0') then
         STATE <= WAIT_FOR_START;
      elsif(clk'event and clk = '1') then
         STATE <= NEXT_STATE;
      end if;
   end process;


process(STATE, start, count, Bin_in)
   begin
      case STATE is
         when WAIT_FOR_START =>
            if start = '1' then
               NEXT_STATE <= LOAD;
            else
               NEXT_STATE <= WAIT_FOR_START;
            end if;
         when LOAD =>
		   if (unsigned(Bin_in) > 99999) THEN
		     NEXT_STATE <= OUTOFRANGE;
		   else
		     NEXT_STATE <= CONVERT;
		   end if;
         when CONVERT =>
            if count = 1 then
               NEXT_STATE <= FINISH;
            else
               NEXT_STATE <= CONVERT;
            end if;
		 when OUTOFRANGE => NEXT_STATE <= WAIT_FOR_START;
		 when FINISH => NEXT_STATE <= WAIT_FOR_START;
         when others => NEXT_STATE <= WAIT_FOR_START;
      end case;
   end process;

process(clk, rst, start)
   begin
      if (start = '1') THEN
		count <= 20;
	  elsif(rst = '0') then
        count <= 20;
      elsif(clk'event and clk = '1') then
         if(conv_en = '1') then
            count <= count - 1;
         end if;
      end if;
   end process;

END Behavioral;