-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : adderseq_tester_flow.vhd                  =
-- = Software: Mentor Graphics Renoir(TM) 2000.3(Build 2)=
-- = Notes   : BikeCom.AdderSeq_tester                   =
-- =======================================================
-- = Datum   : 07.08.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Entity BikeCom.AdderSeq_tester.interface
--

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY AdderSeq_tester IS
   PORT( 
      C_out : IN     std_logic_vector (16 DOWNTO 0) ;
      done  : IN     std_logic  ;
      error : IN     std_logic  ;
      A_in  : OUT    std_logic_vector (16 DOWNTO 0) ;
      B_in  : OUT    std_logic_vector (16 DOWNTO 0) ;
      rst   : OUT    std_logic  ;
      start : OUT    std_logic 
   );

-- Declarations

END AdderSeq_tester ;

--
-- VHDL Architecture BikeCom.AdderSeq_tester.flow
--

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ARCHITECTURE flow OF AdderSeq_tester IS

BEGIN

   ---------------------------------------------------------------------------
   process0 : PROCESS
   ---------------------------------------------------------------------------
   BEGIN
      rst <= '1',
               '0' AFTER 1 ms,
               '1' AFTER 2 ms;
      A_in <= "11111111111111111",
                   "00000000000000000" AFTER 5 ms,
                   "00101100010000000" AFTER 15 ms,
                   "00000000001100111" AFTER 25 ms,
                   "10110101000000000" AFTER 35 ms,
                   "00000001101100000" AFTER 45 ms;
      B_in <= "11111111111111111",
                   "00000000000011100" AFTER 5 ms,
                   "00010110000000000" AFTER 15 ms,
                   "00000000000001011" AFTER 25 ms,
                   "10000010100000000" AFTER 35 ms,
                   "00000000000000000" AFTER 45 ms;
      start <= '0',
                  '1' AFTER 6 ms,
                  '0' AFTER 7 ms,
                  '1' AFTER 16 ms,
                  '0' AFTER 17 ms,
                  '1' AFTER 26 ms,
                  '0' AFTER 27 ms,
                  '1' AFTER 36 ms,
                  '0' AFTER 37 ms,
                  '1' AFTER 45450 us,
                  '0' AFTER 46450 us;
      wait;
   END PROCESS process0;


END flow;