-- University of Applied Sciences / Munich
-- Federal Technological Education Center / Rio de Janeiro
-- =======================================================
-- = Project : Bicycle computer in VHDL                  =
-- = File    : adderseq_behavioral.vhd                   =
-- = Notes   : BikeCom.AdderSeq                          =
-- =======================================================
-- = Datum   : 20.02.2001                                =
-- = Design  : Joachim Reiss                             =
-- = Revision: 001                                       =
-- =======================================================
--
--

--
-- VHDL Architecture BikeCom.AdderSeq.Behavioral
--


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;

entity AdderSeq is
   port (
      clk        : in std_logic;
	  rst        : in std_logic;
	  start      : in std_logic;
	  A_in       : in std_logic_vector(16 downto 0);
	  B_in       : in std_logic_vector(16 downto 0);
	  done       : out std_logic;
	  error      : out std_logic;
	  C_out      : out std_logic_vector(16 downto 0));
end AdderSeq;

architecture behavioral of AdderSeq is

--Registers
signal result  : std_logic_vector(17 downto 0);
signal A       : std_logic_vector(16 downto 0);
signal B       : std_logic_vector(16 downto 0);

--Control signals
signal load_en : std_logic;

--State machine related signals
signal STATE            : std_logic_vector(4 downto 0);
signal NEXT_STATE       : std_logic_vector(4 downto 0);
constant WAIT_FOR_START : std_logic_vector(4 downto 0) := "00001";
constant LOAD           : std_logic_vector(4 downto 0) := "00010";
constant ADD            : std_logic_vector(4 downto 0) := "00100";
constant FINISH         : std_logic_vector(4 downto 0) := "01000";
constant OVERFLOW       : std_logic_vector(4 downto 0) := "10000";


begin

C_out <= result (16 downto 0);
load_en <= STATE(1);
done <= STATE(3);
error <= STATE(4);

process(clk, rst)
   begin
      if (rst = '0') then
         B <= (OTHERS => '0');
      elsif(clk'event and clk = '1') then
         if (load_en = '1') then
            B <= B_in;
         end if;
      end if;
   end process;

process(clk, rst)
   begin
      if (rst = '0') then
         A <= (OTHERS => '0');
      elsif(clk'event and clk = '1') then
         if (load_en = '1') then
            A <= A_in;
         end if;
      end if;
  end process;

process(A, B)
   begin
     result <= ('0' & A) + ('0' & B);
   end process;

process(clk, rst)
   begin
      if(rst = '0') then
         STATE <= WAIT_FOR_START;
      elsif(clk'event and clk = '1') then
         STATE <= NEXT_STATE;
      end if;
   end process;

process(STATE, start, B, Result)
   begin
      case STATE is
         when WAIT_FOR_START =>
            if start = '1' then
               NEXT_STATE <= LOAD;
            else
               NEXT_STATE <= WAIT_FOR_START;
            end if;
         when LOAD => NEXT_STATE <= ADD;
		 when ADD =>
            if Result(17) = '0' then
               NEXT_STATE <= FINISH;
            else
               NEXT_STATE <= OVERFLOW;
            end if;
		 when OVERFLOW => NEXT_STATE <= WAIT_FOR_START;
		 when FINISH => NEXT_STATE <= WAIT_FOR_START;
         when others => NEXT_STATE <= WAIT_FOR_START;
      end case;
   end process;

end behavioral;